SPTS Technologies

Single Wafer Platforms | SPTS

Single Wafer Platforms | Single Wafer Platforms | fxP® Platform | c2L Platform | LPX Platform | Categories | You are now leaving the SPTS website

Technology Papers | SPTS

Technology Papers | "Analysis and Management of the Effects of Fluorinated Gases during Plasma Dicing" Janet Hopkins et al | "Optimization of Low Temperature PECVD Dielectric Stacks for Via Reveal Passivation" K. Crook etc al | "Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration" Anne Jourdain et al | "Exploring the Challenges of Gallium Arsenide Plasma Dicing" M. Day et al | "Improved Semiconductor Device Reliability from Plasma Dicing" R. Barnett et al | "Fan-Out Wafer Processing in the High Density Packaging Era" David Butler et al | "Plasma Dicing: Reducing the cost of singulating thinner, smaller die" O. Ansell | "Plasma Dicing 300mm Framed Wafers - Analysis of Improvement in Die Strength and Cost Benefits for for Thin Die Singulation" M. Blair | "Impact of Backside Processing on C-V Characteristics of TSV Capacitors in 3D stacked IC Process flows" J. de Vos et al | "Improving device yields and throughput using plasma dicing" R. Barnett et al | "Comparison between wet and dry silicon via reveal in 3D backside processing" D. Thomas et al; SPTS/imec joint paper | "Wafer-to-Wafer Metal Sputter Deposition Process Control by Automatic Deposition Rate Adjustment" C. Weng et al | "Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume Production" C Short et al | "Advances in Etch and Deposition Technologies for 2.5 and 3D BEOL Processing" K Buchanan et al | "Claritas™ – A unique and robust endpoint technology for silicon DRIE processes with open area down to 0.05%" O. Ansell et al | "Considerations and Benefits of Plasma Etch Based Wafer Dicing" R. Barnett et al | "Advances in Back-side Via Etching of SiC for GaN Device Applications" A. Barker et al | "Dielectric Stack Engineering for Via-Reveal Passivation" K. Crook et al. | "Low Temperature Dielectric Deposition for Via-Reveal Passivation" K. Crook et al. | "Plasma Etch and Low Temperature PECVD Processes for Via Reveal Applications" D. Thomas et al | "3D Multi-stacking of Thin Die based on TSV and Micro-inserts Interconnections" J. Souriau et al. | "Refractive Index Graded Anti-reflection Coating for Solar Cells Based on Low Cost Reclaimed Silicon" Y. Liu et al. | "Advanced Deep Reactive-Ion Etching (DRIE) Technology for Hollow Microneedles for Transdermal Blood Sampling and Drug Delivery" Y. Liu et al. | "Yield and Productivity Improvements Through Use of Advanced Dual Plasma Source for TSV Reveal & Wafer Dicing Applications" R. Barnett et al. | "300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera’s MVP (TSV) Technology" D.Thomas et al. | Resource Library | You are now leaving the SPTS website